• GSET Engineering - FPGA Developer - VP

    Location(s) US-NY-New York
    Job ID
    Schedule Type
    Full Time
    Associate, Vice President/Executive Director
    Engineering, Technology
    Business Unit
    S3 Trading Technology
    Employment Type



    FPGA Developer with an industry focus in the design of low latency hybrid (software/hardware) systems. In this role the candidate will develop FPGA and software code in support of real-time, production critical financial systems.

    Common Responsibilities:

    • Application development in Verilog and SystemVerilog for Xilinx or Altera FPGA products
    • Rigorous testbench development for all top-level designs and custom developed modules
    • Software development of applications that interface with FPGA (e.g., drivers, monitoring/logging tools, higher level applications)
    • Design and implementation of in-line packet processing and generation modules
    • Support all phases of development activities for FPGA projects, including, but not limited to:
      • Upfront analysis
      • Prototyping
      • Testbench development
      • Development of synthesizable, efficient logic
      • Functional and timing simulation
      • Optimization to meet timing closure and fit on-chip resources
      • Evaluation in lab & collocated test environments
    • Large-scale automated lab testing of developed hardware
    • Analysis of measured data from lab and/or colocation site testing. Comparison of expected performance to actual measured performance

    What We Do

    At Goldman Sachs, our Engineers don’t just make things – we make things possible.  Change the world by connecting people and capital with ideas.  Solve the most challenging and pressing engineering problems for our clients.  Join our engineering teams that build massively scalable software and systems, architect low latency infrastructure solutions, proactively guard against cyber threats, and leverage machine learning alongside financial engineering to continuously turn data into action.  Create new businesses, transform finance, and explore a world of opportunity at the speed of markets.


    Engineering, which is comprised of our Technology Division and global strategists groups, is at the critical center of our business, and our dynamic environment requires innovative strategic thinking and immediate, real solutions.  Want to push the limit of digital possibilities?  Start here.


    Who We Look For

    Goldman Sachs Engineers are innovators and problem-solvers, building solutions in risk management, big data, mobile and more. We look for creative collaborators who evolve, adapt to change and thrive in a fast-paced global environment.


    Required Qualifications:

    • BS and minimum 5 years of industry experience
    • Verilog & SystemVerilog for RTL and synthesis, targeting Xilinx or Altera FPGA platforms
    • SystemVerilog for verification, using knowledge of object-oriented programming techniques
    • Low level software development (kernel modules, drivers, interrupt handlers)
    • Networking – knowledge and development across networks (e.g. TCP, UDP, Ethernet)
    • Serial communications experience
    • Linux experience – environment, software development
    • Excellent organizational skills
    • Ability to prioritize work and maximize productivity

    Preferred Qualifications:

    • Experience with Xilinx UltraScale+ series FPGAs
    • Experience with high speed data buses (e.g. PCIe, 10G-Base-R)
    • Version control experience with git


    The Goldman Sachs Group, Inc. is a leading global investment banking, securities and investment management firm that provides a wide range of financial services to a substantial and diversified client base that includes corporations, financial institutions, governments and individuals. Founded in 1869, the firm is headquartered in New York and maintains offices in all major financial centers around the world.

    © The Goldman Sachs Group, Inc., 2018. All rights reserved Goldman Sachs is an equal employment/affirmative action employer Female/Minority/Disability/Vet.